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PIC16F946
DS41265A-page 266
Preliminary
2005 Microchip Technology Inc.
T
T1CON Register.................................................................. 89
Time-out Sequence........................................................... 196
Timer0
Associated Registers .................................................. 85
External Clock ............................................................. 84
External Clock Requirements ................................... 244
Interrupt....................................................................... 83
Operation .................................................................... 83
T0CKI .......................................................................... 84
Timer0 Module .................................................................... 83
Timer1
Associated Registers .................................................. 91
Asynchronous Counter Mode ..................................... 90
Reading and Writing ........................................... 90
External Clock Requirements ................................... 244
Interrupt....................................................................... 88
Modes of Operations................................................... 88
Operation During Sleep .............................................. 91
Prescaler ..................................................................... 88
Resetting of Timer1 Registers .................................... 91
Resetting Timer1 Using a CCP Trigger Output........... 90
Timer1 Gate
Inverting Gate ..................................................... 88
Selecting Source ........................................... 88, 99
Synchronizing C2OUT w/ Timer1 ....................... 99
TMR1H Register ......................................................... 87
TMR1L Register .......................................................... 87
Timer1 Module with Gate Control ....................................... 87
Timer2 ................................................................................. 93
Associated registers.................................................... 94
Operation .................................................................... 93
Postscaler ................................................................... 93
PR2 Register............................................................... 93
Prescaler ..................................................................... 93
TMR2 Output .............................................................. 94
TMR2 Register ............................................................ 93
TMR2 to PR2 Match Interrupt ............................... 93, 94
Timing Diagrams
A/D Conversion ......................................................... 253
Asynchronous Master Transmission ......................... 138
Asynchronous Master Transmission (Back-to-Back) 138
Asynchronous Reception .......................................... 141
Asynchronous Reception with Address Byte First .... 143
Asynchronous Reception with Address Detect ......... 143
Brown-out Reset (BOR) ............................................ 242
Brown-out Reset Situations ...................................... 195
Capture/Compare/PWM............................................ 245
CLKO and I/O ........................................................... 241
Clock Synchronization .............................................. 182
Comparator Output ..................................................... 96
External Clock ........................................................... 239
Fail-Safe Clock Monitor (FSCM) ................................. 82
I2C Bus Data ............................................................. 251
I2C Bus Start/Stop Bits.............................................. 250
I2C Reception (7-bit Address) ................................... 177
I2C Slave Mode (Transmission, 10-bit Address) ....... 180
I2C Slave Mode with SEN = 0 (Reception,
10-bit Address).................................................. 178
I2C Transmission (7-bit Address) .............................. 179
INT Pin Interrupt........................................................ 204
LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 124
LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 126
Reset, WDT, OST and Power-up Timer ................... 242
Slave Synchronization .............................................. 172
SPI Master Mode (CKE = 1, SMP = 1) ..................... 248
SPI Mode (Master Mode).......................................... 171
SPI Mode (Slave Mode with CKE = 0)...................... 173
SPI Mode (Slave Mode with CKE = 1)...................... 173
SPI Slave Mode (CKE = 0) ....................................... 249
SPI Slave Mode (CKE = 1) ....................................... 249
Synchronous Reception (Master Mode, SREN) ....... 147
Synchronous Transmission ...................................... 145
Synchronous Transmission (Through TXEN) ........... 145
Time-out Sequence
Case 1 .............................................................. 197
Case 2 .............................................................. 197
Case 3 .............................................................. 197
Timer0 and Timer1 External Clock ........................... 243
Timer1 Incrementing Edge ......................................... 88
Two Speed Start-up.................................................... 81
Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 114
Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 116
Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 118
Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 120
Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 122
Type-A/Type-B in Static Drive .................................. 113
Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 115
Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 117
Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 119
Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 121
Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 123
USART Synchronous Receive (Master/Slave) ......... 245
USART Synchronous Transmission (Master/Slave). 244
Wake-up from Interrupt............................................. 209
Timing Parameter Symbology .......................................... 238
Timing Requirements
I2C Bus Data............................................................. 252
I2C Bus Start/Stop Bits ............................................. 251
SPI Mode .................................................................. 250
TMR1H Register ................................................................. 87
TMR1L Register.................................................................. 87
TRISA
Registers .................................................................... 27
TRISA Register................................................................... 28
TRISB
Registers .................................................................... 37
TRISB Register................................................................... 38
TRISC
Registers .................................................................... 47
TRISC Register................................................................... 47
TRISD
Registers .................................................................... 56
TRISD Register................................................................... 56
TRISE
Registers .................................................................... 61
TRISE Register................................................................... 61
TRISF
Registers .................................................................... 65
TRISF Register ................................................................... 65
TRISG
Registers .................................................................... 68
TRISG Register .................................................................. 68
Two-Speed Clock Start-up Mode........................................ 80
TXSTA Register
BRGH Bit .................................................................. 133
CSRC Bit .................................................................. 133
SYNC Bit .................................................................. 133
TRMT Bit................................................................... 133
TX9 Bit ...................................................................... 133
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